In semiconductor wafers utilizing multilayered circuits, damascene metal interconnect lines are used to conduct current through the layers using interconnect structure singularly termed a line and a via. A line is also sometimes referred to as a land and a via is sometimes also referred to as a feed-through hole. These interconnect structure were heretofore usually made of aluminum, but are increasingly being made of copper. Currently, semiconductor technology is moving away from the use of aluminum as the metal of choice in circuitry and toward the use of copper. This move toward the production of copper interconnect structure semiconductors is receiving intense research because copper conducts electricity with lower resistance than aluminum which results in increased microprocessor speed. Additionally, copper uses less power and costs less than aluminum. Also, the physical attributes of copper metal allow for space-saving circuitry design. A discussion of the move toward copper in semiconductor devices can be found in The Electron, "Smokin . . . Watch Out, Fast Computers are on the way Speed is now Pushing Computing Power," by Andy Maslowski, April/May/June 1998, Vol. 25, No.2, pp. 1 and 20. The Electron is published at 4781 E. 355th St., Willoughby, Ohio 44094-4698.
A published article concerning the challenges to industry in making the move to copper interconnects in integrated circuits and a brief teaching of the fundamentals of copper electroplating is an article entitled "Tantalum, Copper, and Damascene: The Future of Interconnects" by Peter Singer, Semiconductor International, June 1998. The challenges have been accepted by industry, but have resulted in copper interconnect structures that need special encapsulating fabrication techniques to overcome the characteristic that copper diffuses into silicon and silicon dioxide and reacts with most metals and suicides such as Al, Ti, CoSi.sub.2, NiSi, and TiSi.sub.2 , which are commonly used in microelectronic devices. See "Electroless CoWP Barrier/Protection Layer Deposition For Cu Metallization", S. Lopatin et al., Material Research Society, 1997, pp. 463-468, "High Aspect Ratio Quarter-micron Electroless Copper Integrated Technology", Yosi Shacham-Diamand et al., Microelectronic Engineering, 1997, pp. 77-88, and U.S. Pat. No. 5,695,810 to Dubin et al.
U.S. Pat. No. 5,695,810 teaches a technique of encapsulating copper circuit interconnect lines in a CoWP (cobalt-tungsten-phosphide) barrier including a capping step with the CoWP material. Other known fabrication techniques include single-Damascene process, or dual-Damascene process. In the single-Damascene process, either the interconnect lines, or the vias, are fabricated separately, while in the dual-Damascene process, both vias and interconnect lines are fabricated concurrently. The dual-Damascene fabrication process has the limitation of requiring high dielectric constant (i.e, high-k) layers that are used to overcome etch-uniformity problems that occur during trench etch fabrication steps. The dual-Damascene fabrication process also has the problem of maintaining adequate seed layer step coverage in designs involving a via or a trench structure whose cross-sectional area has a high aspect ratio (i.e., where the via or trench height to width ratio is at least 3:1). Further, dual-Damascene fabrication problems include concerns about via bottom opening to Cu and cleaning.
Thus, a primary object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic by using selective electroplated copper fabrication techniques.
A related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic which is fabricated such that silicon nitride and silicon dioxide layers are not required.
Another related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that copper interconnect structure in the less that 0.25 .mu.m range is facilitated.
Yet another related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that the copper interconnect structure formed by selective electroplated copper fabrication techniques is encapsulate in metal barriers.
Still another related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that the copper interconnect structure can be formed by with minimal concerns about seed layer step coverage.